Physical Design Engineer
Company: Celestial AI
Location: Irvine
Posted on: February 13, 2026
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Job Description:
Job Description Job Description About Celestial AI As Generative
AI continues to advance, the performance drivers for data center
infrastructure are shifting from systems-on-chip (SOCs) to systems
of chips. In the era of Accelerated Computing, data center
bottlenecks are no longer limited to compute performance, but
rather the system's interconnect bandwidth, memory bandwidth, and
memory capacity. Celestial AI's Photonic Fabric™ is the
next-generation interconnect technology that delivers a tenfold
increase in performance and energy efficiency compared to competing
solutions. The Photonic Fabric™ is available to our customers in
multiple technology offerings, including optical interface
chiplets, optical interposers, and Optical Multi-chip Interconnect
Bridges (OMIB). This allows customers to easily incorporate high
bandwidth, low power, and low latency optical interfaces into their
AI accelerators and GPUs. The technology is fully compatible with
both protocol and physical layers, including standard 2.5D
packaging processes. This seamless integration enables XPUs to
utilize optical interconnects for both compute-to-compute and
compute-to-memory fabrics, achieving bandwidths in the tens of
terabits per second with nanosecond latencies. This innovation
empowers hyperscalers to enhance the efficiency and
cost-effectiveness of AI processing by optimizing the XPUs required
for training and inference, while significantly reducing the TCO2
impact. To bolster customer collaborations, Celestial AI is
developing a Photonic Fabric ecosystem consisting of tier-1
partnerships that include custom silicon/ASIC design, system
integrators, HBM memory, assembly, and packaging suppliers. ABOUT
THE ROLE We are seeking a highly skilled and experienced Physical
Design Engineer to join our team. The ideal candidate will have a
strong background in physical design & physical design
methodologies for both SOC level and block level. They should have
experience that includes floorplanning, hard IP integration, power
distribution, Multi-Supply, Multi-Vt, Clock Tree Synthesis, as well
as timing budgeting, optimization and timing closure of high-speed
designs. Additionally, experience with deep technology nodes such
as 5nm/4nm would be highly valued. ESSENTIAL DUTIES AND
RESPONSIBILITIES Develop and implement high-performance, low-power,
area efficient physical design for SOC and block level designs
using industry standard EDA tools. Work closely with digital and
analog design teams to understand design requirements and
constraints to be able to implement physical design. Contribute to
physical design flow development. Resolve or find workarounds for
tool issues, independently or working with EDA tool vendors. Work
closely with synthesis team to help provide feedback on design
feasibility, constraints, timing, power, placement and routing
issues. Perform physical verification, STA, EM & IR Drop analysis.
QUALIFICATIONS Bachelor's degree in Electrical or Computer
Engineering (advanced degree preferred). Minimum of 5 years of
industry experience in physical design. Knowledge and hands-on
experience with physical design methodologies and implementation.
Proficiency in relevant EDA physical design and verification tools
(e.g., Cadence Innovus, Tempus, Quantus, Voltus, Pegasus) and
scripting languages (e.g., Tcl, Perl). Experience with custom IP
integration. Strong understanding of deep technology nodes,
preferably TSMC N5. Solid understanding of physical design and
timing optimization techniques and strategies to achieve physical
design and timing closure. Proven track record of delivering
successful designs on time and meeting performance, power and area
goals. Excellent problem-solving skills and ability to analyze and
debug complex physical design issues. Strong communication and
collaboration skills to work effectively within cross-functional
teams. PREFERRED QUALIFICATIONS Experience with complex clock tree
synthesis. Knowledge of low-power UPF based physical design flows.
Knowledge of hierarchical physical design flows, for large chips.
Understanding of power-aware optimization techniques for low-power
designs. Understanding process related issues such as OCV, DFM,
yield, multi-vt strategies and thermal management. LOCATION :
Orange County, CA For California Location: As an early stage start
up, we offer an extremely attractive total compensation package
inclusive of competitive base salary, bonus and a generous grant of
our valuable early-stage equity. The target base salary for this
role is approximately $185,000.00 - $215,000.00. The base salary
offered may be slightly higher or lower than the target base
salary, based on the final scope as determined by the depth of the
experience and skills demonstrated by candidate in the interviews.
We offer great benefits (health, vision, dental and life
insurance), collaborative and continuous learning work environment,
where you will get a chance to work with smart and dedicated people
engaged in developing the next generation architecture for high
performance computing. Celestial AI Inc. is proud to be an equal
opportunity workplace and is an affirmative action employer.
LI-Onsite
Keywords: Celestial AI, Azusa , Physical Design Engineer, Engineering , Irvine, California
